Chemical mechanical polishing (CMP) is generally known in the art. For example U.S. Pat. No. 5,177,908 to Tuttle issued in 1993 describes a finishing element for semiconductor wafers, having a face shaped to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer in order to effect improved planarity of the workpiece. U.S. Pat. No. 5,234,867 to Schultz et. al. issued in 1993 describes an apparatus for planarizing semiconductor wafers which in a preferred form includes a rotatable platen for polishing a surface of the workpiece and a motor for rotating the platen and a non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. Fixed abrasive finishing elements are also known for polishing semiconductor layers. An example is WO 98/18159 PCT application by Minnesota Mining and Manufacturing.
Semiconductor wafer fabrication generally requires the formation of layers of material having particularly small thickness. A typical conductor layer, such as a metal layer, is generally 2,000 to 6,000 angstroms thick and a typical insulating layer, for example an oxide layer, is generally 3,000 to 5,000 angstroms thick. The actual thickness is at least partially dependent on the function of the layer along with the function and design of the semiconductor wafer. A gate oxide layer can be less than 100 angstroms while a field oxide is in the thousands of angstroms in thickness. In higher density and higher value semiconductor wafers the layers can be below 500 angstroms in thickness. Generally during semiconductor fabrication, layers thicker than necessary are formed and then thinned down to the required tolerances with techniques needed such as Chemical Mechanical Polishing. Because of the strict tolerances, extreme care is given to attaining the required thinned down tolerances. As such, it is important to accurately determine just when enough of the layer has been removed to reach the required tolerances, this is the end point for the thinning or polishing operation. One method to remove selected amounts of material is to remove the semiconductor wafer periodically from polishing for measurements such as thickness layer measurements. Although this can be done it is time consuming and adds extra expense to the operation. Further the expensive wafers can be damaged during transfer to or from the measurement process further decreasing process yields and increasing costs.